1. Field of the Invention
The present invention relates to an electrically erasable programmable read-only memory (EEPROM) and a method of operating the same, and more particularly, to an EEPROM having a single gate structure and a method of operating the same.
2. Description of Related Art
Various memory cell structures have been suggested for a non-volatile EEPROM device capable of electrically programming and erasing data. In non-volatile memory devices data stored in memory cells is maintained even without a power supply voltage. A typical unit memory cell of an EEPROM has a floating gate, having a stacked gate structure, for storing data and a control gate formed on the floating gate with a dielectric layer interposed therebetween. As electronic devices become smaller and semiconductor device fabricating techniques become more advanced, system on chip (SOC), in which various semiconductor devices are included in one semiconductor chip, has emerged as an important architecture.
In order to fabricate an EEPROM embedded in a SOC, logic devices and the EEPROM are fabricated in the same process. The logic devices of the SOC typically employ a transistor having a single gate structure. Accordingly, an SOC fabrication process for embedding an EEPROM having a stacked gate structure in the SOC is complicated. To simplify the SOC fabrication process, an EEPROM having a single gate structure has been suggested. Employing an EEPROM having a single gate structure allows the SOC to be implemented using a typical complementary metal oxide semiconductor (CMOS) fabrication process which is applied in the fabrication of a logic device.
An EEPROM having a single gate structure includes an access transistor for reading data, and a control gate transistor for data programming. Operation modes of an EEPROM having a single gate structure include programming, reading, and erasing operation modes. In the programming operation mode and the erasing operation mode in which charges are trapped or released in a floating gate via a tunneling gate insulating layer, a high voltage needs to be applied to source/drain regions of the access transistor. However, since, in a typical process of fabricating an EEPROM having a single gate structure, source/drain regions of the EEPROM are formed using a well formed in the CMOS fabricating process, a junction breakdown voltage between the source/drain regions and wells surrounding the source/drain regions is low. Accordingly, there are constraints on applying a high voltage in the programming and erasing operation modes of the EEPROM.